Integrated circuit structure electrically isolated by
a combination of amorphous silicon walls and
isolating pn junction

ABSTRACT

A PLANAR MONOCRYSTALLINE SILICON INTERATED CIRCUIT STRUCTURE HAVING A PLURALITY OF ELECTRICALLY ISOLATED POCKETS EXTENDING FROM THE SILICON SUBSTRATE SURFACE. EACH POCKET IS ISOLATED BY SIDEWALLS OF AMORPHOUS SILICON, FORMED BY THE BOMBARDMENT OF THE SILICON SUBSTRATE WITH SILICON IONS, LATERALLY ENCLOSING AN UPPER PORTION OF THE POCKET AND AN ISOLATING JUNCTION CONTINUOUS WITH SAID SIDEWALLS ENCLOSING THE LOWER PORTION OF THE POCKET. EACH ISOLATED POCKET IS SILICON OF ONE CONDUCTIVITY TYPE, AND SAID ISOLATING JUNCTION IS FORMED BY A SILICON REGION OF OPPOSITE CONDUCTIVITY TYPE ABUTTING THE POCKET. THE POCKETS CONTAIN REGIONS OF ONLY SAID OPPOSITE CONDUCTIVITY TYPE EXTENDING FROM THE SURFACE INTO THE POCKET BUT SPACED FROM SAID SIDEWALLS AND ISOLATING JUNCTIONS. THE STRUCTURE AVOIDS THE PROBLEM OF PARASITIC CAPACITANCES WHICH TEND TO OCCUR IN COMPLETELY JUNCION ISOLATED INTEGRATED CIRCUITS ALONG VERTICAL JUNCTIONS. BY LIMITING THE STRUCTURE TO ONLY REGIONS OF OPPOSITE CONDUCTIVITY TYPE DIFFUSED INTO POCKETS OF SAID ONE CONDUCTIVITY TYPE, THE STRUCTURE AVOIDS VERTICAL PN JUNCTIONS WHICH ARE ADJACENT TO EACH OTHER AND THUS, ARE SUBJECT TO PARASITIC CAPACITANCE EFFECTS.

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at therequest of the applicant or owner in accordance with the Notice of Dec.16, 1969, 869 0.G. 687. The abstracts of Defensive Publicationapplications are identified by distinctly numbered series and arearranged chronologically. The heading of each abstract indicates thenumber of pages of specification, including claims and sheets ofdrawings contained in the application as originally filed. The files ofthese applications are available to the public for inspection andreproduction may he purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to themerits of alleged invention. The Patent Oflice makes no assertion as tothe novelty of the disclosed subject matter.

PUBLISHED JANUARY 1, 197% A planar monocrystafline silicon integratedcircuit structure having a plurality of electrically isolated pocketsextending from the silicon substrate surface. Each pocket is isolated bysidewalls of amorphous silicon, formed by the bombardment of the siliconsubstrate with silicon ions, laterally enclosing an upper portion of thepocket and an isolating junction continuous with said sidewallsenclosing the lower portion of the pocket.

Each isolated pocket is silicon of one conductivity type, and saidisolating junction is formed by a silicon region of oppositeconductivity type abutting the pocket. The pockets contain regions ofonly said opposite conductivity type extending from the surface into thepocket but spaced from said sidewalls and isolating junctions. Thestructure avoids the problem of parasitic capacitanccs which tend tooccur in completely junction isolated integrated circuits along vcrticaljunctions. By limiting the structure to only regions of oppositeconductivity type diffused into pockets of said one conductivity type,the structure avoids vertical PN junctions which are adjacent to eachother and, thus, are subject to parasitic capacitance eifects.

Jan. 1, 1974 K. BRACK ET AL INTEGRATED CIRCUIT STRUCTURE ELECTRICALLYISOLATED BY A COMBINATION OF AMORPHOUS SILICON WALLS AND ISOLATING PNJUNCTION Filed July 27, 1973 V 5) l/ U/ ////7I VT/l:

29 SN W/A

